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E2B0055-19-61 Semiconductor
Semiconductor ML9044
DOT MATRIX LCD CONTROLLER DRIVER
This version: Jun. 1999 ML9044
Pr el im in ar y
GENERAL DESCRIPTION
The ML9044 used in combination with an 8-bit or 4-bit microcontroller controls the operation of a character type dot matrix LCD.
FEATURES
* Easy interfacing with 8-bit or 4-bit microcontroller * Switchable between serial and parallel interfaces * Dot-matrix LCD controller/driver for a small (5 7 dots) or large (5 10 dots) font * Built-in circuit allowing automatic resetting at power-on * Built-in 17 common signal drivers and 120 segment signal drivers * Built-in character generation ROM capable of generating 160 small characters (5 7 dots) or 32 large characters (5 10 dots) * Creation of character patterns by programming: up to 8 small character patterns (5 8 dots) or up to 4 large character patterns (5 11 dots) * Built-in RC oscillation circuit using external or internal resistors * Program-selectable duties: 1/9 duty (1 line: 5 7 dots + cursor + arbitrator), 1/12 duty (1 line: 5 10 dots + cursor + arbitrator), or 1/17 duty (2 lines: 5 7 dots + cursor + arbitrator) * Built-in bias dividing resistors to drive the LCD * Bi-directional transfer of segment outputs * Bi-directional transfer of common outputs * Equipped with a 120-dot arbitrator * Display shifting on each line * Built-in contrast control circuit * Built-in voltage multiplier circuit * Chip (Gold Bump) Product name : ML9044CVWA
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VDD GND OSC1 OSCR OSC2
BLOCK DIAGRAM
Semiconductor
Timing generator 7 Cursor blink controller Instruction decoder (ID) 17-bit shift register Common signal driver COM17 COM1
RS1 RS0 R/W E CS P/S SHT SI SO DB0 to DB3 DB4 to DB7 T1 T2 T3 V1 V2 V3A V3B V4 V5 V5IN 4 4
8
Instruction register (IR)
8
Rarallelserial converter
Character generator RAM (CGRAM)
5
I/O buffer
SEG1 5
8
Data register (DR)
8 8
Character
Segment Signa - driver
generator ROM Address 8 Display data RAM (DDRAM) 5 Arbitrator RAM (ABRAM) (CGROM) counter
120-bit shift register
120-bit latch
Test circuit 8 Busy flag (BF)
(ADC) Expansion
LCD bias voltage dividing circuit 5
Expansion Instruction register (ER) Voltage multiplier circuit
8
Instruction decoder (ED)
SEG120
ML9044
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CSR SSR VCC VC VIN BEB
Semiconductor
ML9044
I/O CIRCUITS
VDD P
P VDD
VDD
VDD P
N
N
N
Applied to pins E, SSR, CSR, BEB, CS P/S, SHT, and SI
Applied to pins T1, T2, and T3
Applied to pins R/W, RS1, and RS0
VDD
VDD
P
P VDD N P
N Output Enable signal Applied to pins DB0 to DB7
VDD
VDD
PP N Output Enable signal Applied to pins SO
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Semiconductor
ML9044
PIN DESCRIPTIONS
Symbol R/W I/F Mode. This pin should be open in the Serial I/F Mode. RS0, RS1 The input pins with a pull-up resistor- to select a register in the Parallel I/F Mode. RS1 H H L E RS0 H L L Name of register Data register Instruction register Expansion Instruction register Description The input pin with a pull-up resistor to select Read ("H") or Write ("L") in the Parallel
This pin should be open in the Serial I/F Mode. The input pin for data input/output between the CPU and the ML9044 and for activating instructions in the Parallel I/F Mode. This pin should be open in the Serial I/F Mode. DB0 to DB3 The input/output pins to transfer data of lower-order 4 bits between the CPU and the ML9044 in the Parallel I/F Mode. Each pin is equipped with a pull-up resistor. These 4 lines are not used for the 4-bit interface. This pin should be open in the Serial I/F Mode. DB4 to DB7 The input/output pins to transfer data of upper 4 bits between the CPU and the ML9044 in the Parallel I/F Mode. Each pin is equipped with a pull-up resistor. This pin should be open in the Serial I/F Mode. OSC1 OSC2 OSCR The clock oscillation pins required for LCD drive signals and the operation of the ML9044 by instructions sent from the CPU. To input external clock, the OSC1 pin should be used. The OSCR and the OSC2 pins should be open. To start oscillation with an external resistor, the resistor should be connected between the OSC1 and OSC2 pins. The OSCR pin should be open. To start oscillation with an internal resistor, the OSC2 and OSCR pins should be short-circuited outside the ML9044. The OSC1 pin should be open. COM1 to COM17 The LCD common signal output pins. For 1/9 duty, non-selectable voltage waveforms are output via COM10 to COM17. For 1/12 duty, non-selectable voltage waveforms are output via COM13 to COM17. SEG1 to SEG120 The LCD segment signal output pins.
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Semiconductor
ML9044
Symbol CSR
Description The input pin to select the transfer direction of the common signal output data. Refer to the Expansion Instruction Codes section about the AS bit. CSR L L L L L L H H H H H H duty 1/9 1/9 1/12 1/12 1/17 1/17 1/9 1/9 1/12 1/12 1/17 1/17 AS bit L H L H L H L H L H L H shift direction COM1 AE COM9 COM2 AE COM9, COM1 COM1 AE COM12 COM2 AE COM12, COM1 COM1 AE COM17 COM2 AE COM17, COM1 COM9 AE COM1 COM8 AE COM1, COM9 COM12 AE COM1 COM11 AE COM1, COM12 COM17 AE COM1 COM16 AE COM1, COM17 arbitrator's common pin COM9 COM1 COM12 COM1 COM17 COM1 COM1 COM9 COM1 COM12 COM1 COM17
SSR
The input pin to select the transfer direction of the segment signal output data. "L": Data transfer from SEG1 to SEG120 "H": Data transfer from SEG120 to SEG1
V1, V2, V3A, V3B, V4
The pins to output bias voltages to the LCD. For 1/4 bias : The V2 and V3B pins are shorted. For 1/5 bias : The V3A and V3B pins are shorted.
BEB
The input pin to enable or disable the voltage multiplier circuit. "L" disables the voltage multiplier circuit. "H" enables the voltage multiplier circuit. The voltage multiplier circuit doubles the input voltage VIN and outputs it to the V5IN pin. The voltage multiplier circuit can be used only when generating a level lower than GND.
VIN V5, V5IN
The pin to input voltage to the voltage multiplier. The pins to supply the LCD drive voltage. The LCD drive voltage is supplied to the V5 pin when the voltage multiplier is not used (BEB = 0) and the internal contrast adjusting circuit is also not used. At this time, the V5IN pin should be open. The LCD drive voltage is supplied to the V5IN pin when the voltage multiplier is not used (BEB = 0) but the internal contrast adjusting circuit is used. At this time, the V5 pin should be open. When the voltage multiplier is used (BEB = 1), the V5IN and V5 pins should be open (the multiplied voltage is output to the V5IN pin). In this case, the internal contrast adjusting circuit is used automatically.
VC VCC
The pin to connect the positive pin of the capacitor for the voltage multiplier. The pin to connect the negative pin of the capacitor used for the voltage multiplier.
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Semiconductor
ML9044
Symbol T1, T2, T3 VDD GND P/S The power supply pin. The ground level input pin.
Description The input pins for test circuits (normally open). Equipped with a pull-down resistor.
The input pin to select the parallel or serial interface. "L" selects the parallel interface. "H" selects the serial interface.
CS
The pin to enable this IC in the serial I/F mode. "L" enables this IC. "H" disables this IC. This pin should be open in the parallel I/F mode.
SHT
The pin to input shift clock in the serial I/F mode. Data inputting to the SI pin is carried out synchronizing with the rising edge of this clock signal. Data outputting from the SO pin is carried out synchronizing with the falling edge of this clock signal. This pin should be open in the parallel I/F mode.
SI
The pin to input DATA in the serial I/F mode. Data inputting to this pin is carried out synchronizing with the rising edge of the SHT signal. This pin should be open in the parallel I/F mode.
SO
The pin to output DATA in the serial I/F mode. Data inputting to this pin is carried out synchronizing with the falling edge of the SHT signal. This pin should be open in the parallel I/F mode.
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Semiconductor
ML9044
ABSOLUTE MAXIMUM RATINGS
Parameter Supply Voltage LCD Driving Voltage Symbol VDD V1, V2, V3, V4, V5 Condition Ta = 25C Ta = 25C Rating -0.3 to +6.5 VDD - 7.5 to VDD+0.3 Unit V V
(GND = 0V) Applicable pins VDD - GND V1, V4, V5, V5IN, V2, V3A, V3B R/W, E, SHT, CSR, P/S, SSR, SI, RS0,
Input Voltage
VI
Ta = 25C
-0.3 to VDD+0.3
V
RS1, BEB, CS, T1 to T3, DB0 to DB7, VIN
Storage Temperature
TSTG
--
-55 to +125
C
--
RECOMMENDED OPERATING CONDITIONS
Parameter Supply Voltage LCD Driving Voltage Input Voltage Operating Temperature Symbol VDD VDD-V5 (See Note) VIN Top Condition -- -- BEB = 1 -- Range 2.5 to 5.5 2.8 to 7.0 VDD-1.40 to VDD-3.5 -40 to +85
(GND = 0V) Unit Applicable pins V V V C VDD-GND VDD-V5 (V5IN) VDD-VIN --
Note:
This voltage should be applied across VDD and V5. The following voltages are output to the V1, V2, V3A (V3B) and V4 pins: * 1/4 bias V1 = {VDD-(VDD-V5)/4} 0.15V V2 = V3B= {VDD-(VDD-V5)/2} 0.15V V4 = {VDD-3 (VDD-V5)/4 } 0.15V * 1/5 bias V1 = {VDD-(VDD-V5)/5} 0.15V V2 = {VDD-2 (VDD-V5)/5} 0.15V V3A = V3B= {VDD-3 (VDD-V5)/5} 0.15V V4 = {VDD-4 (VDD-V5)/5} 0.15V The voltages at the V1, V2, V3A (V3B), V4 and V5 pins should satisfy VDD>V1>V2>V3A(V3B)>V4>V5. (Higher AE Lower) * Do not apply short-circuiting across output pins and across an output pin and an input/output pin or the power supply pin in the output mode.
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Semiconductor
ML9044
ELECTRICAL CHARACTERISTICS
DC Characteristics
Parameter "H" Input Voltage 1 "L" Input Voltage 1 "H" Input Voltage 2 "L" Input Voltage 2 "L" Output Voltage 1 "L" Output Voltage 2 COM Voltage Drop Symbol VIH1 VIL1 VIH2 VIL2 IOH = -0.1mA IOL = +0.1mA IOH = -13mA IOL = +13mA IOCH = -4mA VDD - V5 = 5V IOCMH = 4mA IOCML = 4mA IOCL = +4mA IOSH = -4mA VDD - V5 = 5V IOSMH = 4mA IOSML = 4mA IOSL = +4mA VDD = 5V, VIN = 5V or 0V VDD = 5V, VIN = GND VDD = 5V, VIN = VDD, Excluding current flowing through the pull-up resistor and the output driving MOS Input Current 2 | II2| VDD = 5V, VIN = VDD VDD = 5V, VIN = VDD, Excluding current flowing through the pull-down resistor Supply Current LCD Bias Resistor
Oscillation Frequency of External Resistor Rf Oscillation Frequency of Internal Resistor Rf
(GND = 0V, VDD = 2.5V to 5.5V, Ta = -40 to +85C) Condition -- Min 0.8VDD -0.3 -- 0.8VDD -0.3 0.75VDD -- 0.9VDD -- VDD - 0.3 V4 - 0.3 V5 VDD - 0.3 V3 - 0.3 V5 -- 10 -- -- 25 -- Note 1 V2 - 0.3 Note 1 V1 - 0.3 Typ -- -- -- -- -- -- -- -- Max VDD 0.2VDD VDD 0.2VDD -- 0.2VDD -- 0.1VDD VDD V1 + 0.3 V4 + 0.3 V5 + 0.3 VDD V2 + 0.3 V3 + 0.3 V5 + 0.3 1.0 61 2.0 mA mA
E, SSR, CSR, BEB,
Unit V
Applicable pin R/W, RS0, RS1, E, DB0 to DB7 SHT, P/S, SI, CS
V V V V
OSC1, SSR, CSR, BEB DB0 to DB7, SO OSC2 COM1 to COM17
"H" Output Voltage 1 VOH1 VOL1 VOL2 VCH VCMH VCML VCL SEG Voltage Drop VSH VSMH VSML VSL Input Leakage Current Input Current 1 | II1| | IIL | "H" Output Voltage 2 VOH2
V
SEG1 to SEG120
SHT, P/S, CS, SI R/W, RS0, RS1 DB0 to DB7, SO
15 --
45 --
105 2.0
mA
T1, T2, T3
IDD RLB fosc1 fosc2 fin fduty frf fff
VDD = 5V
Note 2
--
-- 4.0
1.2
mA kW
VDD - GND VDD, V1, V2 V3A, V3B, V4, V5 OSC1, OSC2 OSC1, OSC2, OSCR OSC1
Rf = 120kW2% OSC1: Open OSC2, OSCR: Open Input from OSC1
Note 3 Note 4
175 140 125
270 270
350 480 480
kHz kHz kHz % mS mS
OSC2 and OSCR: Short-circuited
External Clock
Clock Input Frequency
Input Clock Duty
Input Clock Rise Time
Note 5 Note 6 Note 6
45 -- --
50 -- --
55 0.2 0.2
Input Clock Fall Time
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Semiconductor
ML9044
(GND = 0V, VDD = 2.5V to 5.5V, Ta = -40 to +85C) Parameter Control Range of LCD Driving Voltage (by internal variable resistor)
Bias Voltage for Driving LCD by External Input
Symbol VLCD MAX VLCD MIN VLCD1 VLCD2
Condition VDD = 5V, 1/5 bias V5IN = 0V VDD = 5V, 1/5 bias V5IN = 0V VDD - V5 1/5 bias
Min TBD
Typ -- --
Max
Unit
Applicable pin VDD - V5
TBD 7.0 7.0 VDD - 2VIN +1.2V VDD/2 V VIN V V5, V5IN V V5
2.8 2.8 VDD - 2VIN
-- -- --
Note 7 1/4 bias BEB = H
Voltage Multiplier Output Voltage Voltage Multipler Input Voltage
V5OUT VDD = 3V, VIN = 0V VIN
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Semiconductor Note 1:
ML9044
Applied to the voltage drop occurring between any of the VDD, V1, V4 and V5 pins and any of the common pins (COM1 to COM17) when the current of 4mA flows in or flows out at one common pin. Also applied to the voltage drop occurring between any of the VDD, V2, V3A (V3B) and V5 pins and any of the segment pins (SEG1 to SEG120) when the current of 4mA flows in or flows out at one common pin. The current of 4mA flows out when the output level is VDD or flows in when the output level is V5.
Note 2:
Applied to the current flowing into the VDD pin when the external clock (fosc2 = fin = 270 kHz) is fed to the internal Rf oscillation or OSC1 under the following conditions: VDD = 5V GND = V5 = 0V, V1, V2, V3A (V3B) and V4: Open E, SSR, CSR, and BEB: "L" (fixed) Other input pins: "L" or "H" (fixed) Other output pins: No load
Note 3:
Note 4:
OSC1 OSC1 OSCR OSC2 Rf = 120kW2% OSCR
OSC2
The wire between OSC1 and Rf and the wire between OSC2 and Rf should be as short as possible. Keep OSCR open.
The wire between OSC2 and OSCR should be as short as possible. Keep OSC1 open.
Note 5:
tHW tLW
VDD 2 fIN waveform
VDD 2
VDD 2
Applied to the pulses entering from the OSC1 pin fduty = tHW/ (tHW + tLW) 100 (%)
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Semiconductor Note 6:
0.7VDD 0.3VDD 0.7VDD 0.3VDD
ML9044
trf
tff
Applied to the pulses entering from the OSC1 pin
Note 7:
For 1/4 bias, V2 and V3B pins are short-circuited. V3A pin is open. For 1/5 bias, V3A and V3B pins are short-circuited. V2 pin is open.
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Semiconductor
ML9044
Switching Characteristics (The following ratings are subject to change after ES evaluation.) * Parallel Interface Mode The timing for the input from the CPU (see 1) and the timing for the output to the CPU (see 2) are as shown below: 1) WRITE MODE (Timing for input from the CPU)
(VDD = 2.5 to 5.5V, Ta = -40 to +85C) Parameter R/W, RS0, RS1 Setup time E Pulse Width R/W, RS0, RS1 Hold time E Rise Time E Fall Time E Pulse Width E Cycle Time DB0 to DB7 Input Data Hold time DB0 to DB7 Input Data Setup time Symbol tB tW tA tr tf tL tC tI tH Min 40 450 10 -- -- 430 1000 195 10 Typ -- -- -- -- -- -- -- -- -- Max -- -- -- 25 25 -- -- -- -- Unit ns ns ns ns ns ns ns ns ns
RS1, RS0
VIH VIL
VIH VIL
R/W
VIL tB tL tr VIH VIL tI tW tf VIH VIL tH Input Data
VIL tA
E
VIL
DB0 to DB7 tc
VIH VIL
VIH VIL
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Semiconductor 2) READ MODE (Timing for output to the CPU)
ML9044
(VDD = 2.5 to 5.5V, Ta = -40 to +85C) Parameter R/W, RS1, RS0 Setup Time E Pulse Width R/W, RS1, RS0 Hold Time E Rise Time E Fall Time E Pulse Width E Cycle Time DB0 to DB7 Output Data Delay Time DB0 to DB7 Output Data Hold Time Symbol tB tW tA tr tf tL tC tD tO Min 40 450 10 -- -- 430 1000 -- 20 Typ -- -- -- -- -- -- -- -- -- Max -- -- -- 25 25 -- -- 350 -- Unit ns ns ns ns ns ns ns ns ns
RS1, 0
VIH VIL
VIH VIL
R/W
VIH tB tL tr VIH VIL tD VOH VOL tc Output Data tW tf VIH VIL tO
VIH tA
E
VIL
DB0 to DB7
VOH VOL
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Semiconductor * Serial Interface Mode
ML9044
(VDD = 2.5 to 5.5V, Ta = -40 to +85C) Parameter SHT Cycle Time CS Setup Time CS Hold Time SHT Setup Time SHT Hold Time SHT "H" Pulse Width SHT "L" Pulse Width SHT Rise Time SHT Fall Time SI Setup Time SI Hold Time Data Output Delay Time Data Output Hold Time Symbol tSCY tCSU tCH tSSU tSH tSWH tSWL tSR tSF tDISU tDIH tDOD tCDH Min 500 100 100 60 200 200 200 -- -- 100 100 -- 0 Typ -- -- -- -- -- -- -- -- -- -- -- -- -- Max -- -- -- -- -- -- -- 50 50 -- -- 160 -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
tSCY CS tCSU SHT VIL tSSU VIH tSWL tSR VIH tDIH VIH VIL tDOD VOH tCDH VOH tSWH VIH tSF tSH VIH tCH
VIL tDISU VIH VIL tDOD
VIL
SI
SO
VOL
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Semiconductor
ML9044
FUNCTIONAL DESCRIPTION
Instruction Register (IR), Data Register (DR), and Expansion Instruction Register (ER) These registers are selected by setting the level of the Register Selection input pins RS0 and RS1. The DR is selected when both RS0 and RS1 are "H". The IR is selected when RS0 is "L" and RS1 is "H". The ER is selected when both RS0 and RS1 are "L". (When RS0 is "H" and RS1 is "L", the ML9044 is not selected.) The IR stores an instruction code and the address code of the display data RAM (DDRAM) or the character generator RAM (CGRAM). The microcontroller (CPU) can write to the IR but cannot read from the IR. The ER stores a contrast adjusting code and the address code of the arbitrator RAM (ABRAM). The CPU can write to or read from the ER. The DR stores data to be written in the DDRAM, ABRAM and CGRAM and also stores data read from the DDRAM, AMRAM and CGRAM. The data written in the DR by the CPU is automatically written in the DDRAM, ABRAM or CGRAM. When an address code is written in the IR or ER, the data of the specified address is automatically transferred from the DDRAM, ABRAM or CGRAM to the DR. The data of the DDRAM, ABRAM and CGRAM can be checked by allowing the CPU to read the data stored in the DR. After the CPU writes data in the DR, the data of the next address in the DDRAM, ABRAM or CGRAM is selected to be ready for the next writing by the CPU. Similarly, after the CPU reads the data in the DR, the data of the next address in the DDRAM, ABRAM or CGRAM is set in the DR to be ready for the next reading by the CPU. Writing in or reading from these 3 registers is controlled by changing the status of the R/ W(Read/Write) pin.
Table 1 R/W pin status and register operation
R/W L H L H L H RS0 L L H H L L RS1 H H H H L L Writing in the IR Reading the Busy flag (BF) and the address counter (ADC) Writing in the DR Reading from the DR Writing in the ER Reading the contrast code Operation
Busy Flag (BF) The status "1" of the Busy Flag (BF) indicates that the ML9044 is carrying out internal operation. When the BF is "1", any new instruction is ignored. When R/W = "H", RS0 = "L" and RS1 = "H", the data in the BF is output to the DB7. New instructions should be input when the BF is "0". When the BF is "1", the output code of the address counter (ADC) is undefined.
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Semiconductor
ML9044
Address Counter (ADC) The address counter provides a read/write address for the DDRAM, ABRAM or CGRAM and also provides a cursor display address. When an instruction code specifying DDRAM, ABRAM or CGRAM address setting is input to the pre-defined register, the register selects the specified DDRAM, ABRAM or CGRAM and transfers the address code to the ADC. The address data in the ADC is automatically incremented (or decremented) by 1 after the display data is written in or read from the DDRAM, ABRAM or CGRAM. The data in the ADC is output to DB0 to DB6 when R/W = "H", RS0 = "L", RS1 = "H" and BF = "0". Timing Generator The timing generator generates timing signals for the internal operation of the ML9044 activated by the instruction sent from the CPU or for the operation of the internal circuits of the ML9041 such as DDRAM, ABRAM, CGRAM and CGROM. Timing signals are generated so that the internal operation carried out for LCD displaying will not be interfered by the internal operation initiated by accessing from the CPU. For example, when the CPU writes data in the DDRAM, the display of the LCD not corresponding to the written data is not affected.
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Semiconductor
ML9044
Display Data RAM (DDRAM) This RAM stores the display data represented in 8-bit character coding (see Table 2). The DDRAM addresses correspond to the display positions (digits) of the LCD as shown below. The DDRAM addresses (to be set in the ADC) are represented in hexadecimal.
DB6 DB5 DB4 DB3 DB2 DB1 DB0 ADC
MSB LSB
Hexadecimal (Example) Representation of DDRAM address = 12 ADC 0 0 1 1
Hexadecimal
0
0 2
1
0
1) Relationship between DDRAM addresses and display positions (1-line display mode)
Digit 12
3
4
5
23 24 16 17 Right end
Display position DD RAM address (hexadecimal)
00 01 02 03 04 Left end
In the 1-line display mode, the ML9044 can display up to 24 characters from digit 1 to digit 24. While the DDRAM has addresses "00" to "4F" for up to 80 character codes, the area not used for display can be used as a RAM area for general data. When the display is shifted by instruction, the relationship between the LCD display and the DDRAM address changes as shown below:
Digit 12
3
4
23 24 15 16
(Display shifted to the right) 4 F 0 0 0 1 0 2
Digit 12 (Display shifted to the left)
3
4
5
23 24 17 18
01 02 03 04 05
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Semiconductor
ML9044
2) Relationship between DDRAM addresses and display positions (2-line display mode) In the 2-line mode, the ML9044 can display up to 48 characters (24 characters per line) from digit 1 to digit 24.
Digit 12345 Line 1 0 0 0 1 0 2 0 3 0 4 Line 2 4 0 4 1 4 2 4 3 4 4
23 24 16 17 56 57
Display position DD RAM address (hexadecimal)
Note: The DDRAM address at digit 24 in the first line is not consecutive to the DDRAM address at digit 1 in the second line. When the display is shifted by instruction, the relationship between the LCD display and the DDRAM address changes as shown below:
(Display shifted to the right)
Digit 12345 Line 1 2 7 0 0 0 1 0 2 0 3 Line 2 6 7 4 0 4 1 4 2 4 3 Digit 12345 Line 1 0 1 0 2 0 3 0 4 0 5 Line 2 4 1 4 2 4 3 4 4 4 5
23 24 15 16 55 56
(Display shifted to the left)
23 24 17 18 57 58
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Semiconductor
ML9044
Character Generator ROM (CGROM) The CGROM generates small character patterns (5 7 dots, 160 patterns) or large character patterns (5 10 dots, 32 patterns) from the 8-bit character code signals in the DDRAM. See Table 2 for the relationship between the 8-bit character codes and the character patterns. When the 8-bit character code corresponding to a character pattern in the CGROM is written in the DDRAM, the character pattern is displayed in the display position specified by the DDRAM address.
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Semiconductor Character Generator RAM (CGRAM)
ML9044
The CGRAM is used to generate user-specific character patterns that are not in the CGROM. CGRAM (64 bytes = 512 bits) can store up to 8 small character patterns (5 8 dots) or up to 4 large character patterns (5 11 dots). When displaying a character pattern stored in the CGRAM, write an 8-bit character code (00 to 07 or 08 to 0F; hex.) assigned in Table 2 to the DDRAM. This enables outputting the character pattern to the LCD display position corresponding to the DDRAM address. The cursor or blink is also displayed even when a CGRAM or ABRAM address is set in the ADC. Therefore, the cursor or blink display should be inhibited while the ADC is holding a CGRAM or ABRAM address. The following describes how character patterns are written in and read from the CGRAM. 1) Small character patterns (5 8 dots) (See Table 3-1.) (1) A method of writing character patterns to the CGRAM from the CPU The three CGRAM address bits 0 to 2 select one of the lines constituting a character pattern. First, set the mode to increment or decrement from the CPU, and then input the CGRAM address. Write each line of the character pattern code in the CGRAM through DB0 to DB7. The data lines DB0 to DB7 correspond to the CGRAM data bits 0 to 7, respectively (see Table 3.1). Input data "1" represents the ON status of an LCD dot and "0" represents the OFF status. Since the ADC is automatically incremented or decremented by 1 after the data is written to the CGRAM, it is not necessary to set the CGRAM address again. The bottom line of a character pattern (the CGRAM address bits 0 to 2 are all "1", which means 7 in hexadecimal) is the cursor line. The ON/OFF pattern of this line is ORed with the cursor pattern for displaying on the LCD. Therefore, the pattern data for the cursor position should be all zeros to display the cursor. Whereas the data given by the CGRAM data bits 0 to 4 is output to the LCD as display data, the data given by the CGRAM data bits 5 to 7 is not. Therefore, the CGRAM data bits 5 to 7 can be used as a RAM area. (2) A method of displaying CGRAM character patterns on the LCD The CGRAM is selected when the higher-order 4 bits of a character code are all zeros. Since bit 3 of a character code is not used, the character pattern "0" in Table 3-1 can be selected using the character code "00" or "08" in hexadecimal. When the 8-bit character code corresponding to a character pattern in the CGRAM is written to the DDRAM, the character pattern is displayed in the display position specified by the DDRAM address. (The DDRAM data bits 0 to 2 correspond to the CGRAM address bits 3 to 5, respectively.)
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Semiconductor 2) Large character patterns (5 11 dots) (See Table 3-2.) (1) A method of writing character patterns to the CGRAM from the CPU
ML9044
The four CGRAM address bits 0 to 3 select one of the lines constituting a character pattern. First, set the mode to increment or decrement from the CPU, and then input the CGRAM address. Write each line of the character pattern code in the CGRAM through DB0 to DB7. The data lines DB0 to DB7 correspond to the CGRAM data bits 0 to 7, respectively (see Table 3- 2). Input data "1" represents the ON status of an LCD dot and "0" represents the OFF status. Since the ADC is automatically incremented or decremented by 1 after the data is written to the CGRAM, it is not necessary to set the CGRAM address again. The bottom line of a character pattern (the CGRAM address bits 0 to 3 are all "1", which means A in hexadecimal) is a cursor line. The ON/OFF pattern of this line is ORed with the cursor pattern for displaying on the LCD. Therefore, the pattern data for the cursor position should be all zeros to display the cursor. Whereas the data given by the CGRAM data bits 0 to 4 with the CGRAM addresses 0 to A in hexadecimal (set by the CGRAM address bits 0 to 3) is output as display data to the LCD, the data given by the CGRAM data bits 5 to 7 or the CGRAM addresses B to F in hexadecimal is not. These bits can be written and read as a RAM area. (2) A method of displaying CGRAM character patterns on the LCD The CGRAM is selected when the higher-order 4 bits of a character code are all zeros. Since bits 0 and 3 of a character code are not used, the character pattern "b" in Table 3-2 can be selected with a character code "00", "01", "08" or "09" in hexadecimal. When the 8-bit character code corresponding to a character pattern in the CGRAM is written to the DDRAM, the character pattern is displayed in the display position specified by the DDRAM address. (The DDRAM data bits 1 and 2 correspond to the CGRAM address bits 4 and 5, respectively.)
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Semiconductor
ML9044
Arbitrator RAM (ABRAM) The arbitrator RAM(ABRAM) stores arbitrator display data. The ABRAM address is set at the ADC with the relationship illustrated below. Its valid address area is 00 to 23 (00H to 17H). Although an address exceeding 23 (17H) can be set or the address already set may exceed it due to automatic increment or decrement processing, any address out of the valid address area is ignored. The cursor or blink is also displayed even when a CGRAM or ABRAM address is set in the ADC. Therefore, the cursor or blink display should be inhibited while the ADC is hoding a CGRAM or ABRAM address.
DB6 DB5 DB4 DB3 DB2 DB1 DB0 ADC
MSB LSB
Hexadecimal
Hexadecimal
The arbitrator RAM can store a maximum of 120 dots of the arbitrator Display-ON data in units of 5 dots. The arbitrator display is not shifted by any instructions and has the following relationship with the LCD display positions:.
Configuration of input display data Input data DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
* * * E4 E3 E2 E1 E0 *Don't Care
Relationship between display-ON data and segment pins 5XSn+1 5XSn+5
Display - ON data E4 Sn = ABRAM address (0 to 23) E4
22/54
Semiconductor
Table 2 Relationship between character codes and character patterns of the ML9044
Lower 4 bits Upper 4 bits MSB 0000
0010
0011
0100
0101
0110
0111
1010
1011
1100
1101
1110
1111
0000 LSB 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110
CG RAM (1) (2) (3) (4) (5) (6) (7) (8) (1) (2) (3) (4) (5) (9) (7) (8) - . / ( ) * + # $ % & !
0 1 2 3 4 5 6 7 8 9 : ; < = > ?
@ A B C D E F G H I J K L M N O
P Q R S T U V W X Y Z [ ] ^ _
/ a b c d e f n h i j k l m n o
p q r s t u v w x y z { U } AE
a a b e m s r g -1
j
R q Q * W u S p X
x n o /
ML9044
23/54
1111
Semiconductor Table 3-1
ML9044
Relationship between CGRAM address bits, CGRAM data bits (character pattern) and DDRAM data bits (character code) in 5 7 dot character mode. (Examples)
CG RAM
address
CG RAM data (Character pattern) 76543210
LSB
DD RAM data
MSB
(Character code) LSB
543210
MSB
76543210
0000 0 0 0 1 1 1 1 0010 0 0 0 1 1 1 1 1110 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
LSB MSB
0 01110 1 10001 0 10001 1 10001 0 10001 1 10001 0 01110 1 00000 0 10001 1 10010 0 10100 1 11000 0 10100 1 10010 0 10001 1 00000 0 01110 1 00100 0 00100 1 00100 0 00100 1 00100 0 01110 1 00000
0000000
0000001
0000111
: Don't Care
24/54
Semiconductor Table 3-2
ML9044
Relationship between CGRAM address bits, CGRAM data bits (character pattern) and DDRAM data bits (character code) in 5 10 dot character mode (Examples)
CG RAM
address
CG RAM data (Character pattern)
76543210
LSB
DD RAM data
MSB
(Character code) LSB
543210
MSB
76543210
LSB MSB
000 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 000 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 000 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 01000 1 01111 0 10010 1 01111 0 01 0 10 1 11111 0 00010 1 00000 0 00000 1 00000 0 00000 1 0 1 0 1 0 00000 00000 1 01111 0 10001 1 10001 0 10001 1 01111 0 00001 1 00001 0 01110 1 00000 0 1 0 1 0 1 0 00000 00000 1 0 11011 1 01010 0 10001 1 10001 0 01110 1 00000 0 00000 1 00000 0 00000 1 0 1 0 1
000000
000000
000011
: Don't Care
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Semiconductor
ML9044
Cursor/Blink Control Circuit This circuit generates the cursor and blink of the LCD. The operation of this circuit is controlled by the program of the CPU. The cursor/blink display is carried out in the position corresponding to the DDRAM address set in the ADC (Address Counter). For example, when the ADC stores a value of "07" (hexadecimal), the cursor or blink is displayed as follows:
DB6 ADC 0 00 0 Digit 12 In 1-line display mode 0 1 1 7 DB0 1
3
4
5
6
7
8
9
23 24 16 17
00 01 02 03 04 05 06 07 08
Cursor/blink position
Digit 12 In 2-line display mode First line
3
4
5
6
7
8
9
23 24 16 17 56 57
00 01 02 03 04 05 06 07 08
Second line 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8
Cursor/blink position
Note:
The cursor or blink is also displayed even when a CGRAM or ABRAM address is set in the ADC. Therefore, the cursor or blink display should be inhibited while the ADC is holding a CGRAM or ABRAM address.
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Semiconductor LCD Display Circuit (COM1 to COM17, SEG1 to SEG120, SSR and CSR)
ML9044
The ML9044 has 17 common signal outputs and 120 segment signal outputs to display 24 characters (in the 1-line display mode) or 48 characters (in the 2-line display mode). The character pattern is converted into serial data and transferred in series through the shift register. The transfer direction of serial data is determined by the SSR pin. The shift direction of common signals is determined by the CSR pin. The following tables show the transfer and shift directions:
SSR L H CSR L L L L L L H H H H H H duty 1/9 1/9 1/12 1/12 1/17 1/17 1/9 1/9 1/12 1/12 1/17 1/17
Transfer direction SEG1 AE SEG120 SEG120 AE SEG1 AS bit L H L H L H L H L H L H Shift direction COM1 AE COM9 COM2 AE COM9, COM1 COM1 AE COM12 COM2 AE COM12, COM1 COM1 AE COM17 COM2 AE COM17, COM1 COM9 AE COM1 COM8 AE COM1, COM9 COM12 AE COM1 COM11 AE COM1, COM12 COM17 AE COM1 COM16 AE COM1, COM17 arbitrator's common pin COM9 COM1 COM12 COM1 COM17 COM1 COM1 COM9 COM1 COM12 COM1 COM17
* Refer to the Expansion Instruction Codes section about the AS bit. Signals to be input to the SSR and CSR pins should be determined at power-on and be kept unchanged.
27/54
Semiconductor Built-in Reset Circuit
ML9044
The ML9044 is automatically initialized when the power is turned on. During initialization, the Busy Flag (BF) is "1" and the ML9041 does not accept any instruction from the CPU (other than the Read BF instruction). The Busy Flag is "1" for about 15 ms after the VDD becomes 2.5 V or higher. During this initialization, the ML9044 performs the following instructions: 1) 2) 3) 4) 5) 6) 7) 8) 9) 10) 11) Display clearing CPU interface data length = 8 bits (DL = "1") 1-line LCD display (N = "0") Font size = 5 7 dots (F = "0") ADC counting = Increment (I/D = "1") Display shifting = None (S = "0") Display = Off (D = "0") Cursor = Off (C = "0") Blinking = Off (B = "0") Arbitrator = Displayed in the lower line (AS = "0") Setting 1FH (hexadecimal) to the Contrast Data
To use the built-in reset circuit, the power supply conditions shown below should be satisfied. Otherwise, the built-in reset circuit may not work properly. In such a case, initialize the ML9044 with the instructions from the CPU. The use of a battery always requires such initialization from the CPU. (See "Initial Setting of Instructions")
2.5V
0.2V tON 0.1ms tON 100ms
0.2V tOFF 1ms tOFF
0.2V
Figure 1 Power-on and Power-off Waveform
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Semiconductor I/F with CPU
ML9044
Parallel interface mode The ML9044 can transfer either 8 bits once or 4 bits twice on the data bus for interfacing with any 8-bit or 4-bit microcontroller (CPU). 1) 8-bit interface data length The ML9044 uses all of the 8 data bus lines DB0 to DB7 at a time to transfer data to and from the CPU. 2) 4-bit interface data length The ML9044 uses only the higher-order 4 data bus lines DB4 to DB7 twice to transfer 8-bit data to and from the CPU. The ML9044 first transfers the higher-order 4 bits of 8-bit data (DB4 to DB7 in the case of 8-bit interface data length) and then the lower-order 4 bits of the data (DB0 to DB3 in the case of 8-bit interface data length). The lower-order 4 bits of data should always be transferred even when only the transfer of the higher-order 4 bits of data is required. (Example: Reading the Busy Flag) Two transfers of 4 bits of data complete the transfer of a set of 8-bit data. Therefore, when only one access is made, the following data transfer cannot be completed properly.
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Semiconductor
ML9044
RS1 RS0 R/W E
Busy (Internal operation)
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
IR7 IR6 IR5 IR4 IR3 IR2 IR1 IR0
Busy
No Busy ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0
DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0
Writing In IR (Instruction Register)
Reading BF (Busy Flag) and ADC (Address Counter)
Writing In DR (Data Register)
Figure 2 8-Bit Data Transfer
RS1 RS0 R/W E
Busy (Internal operation)
DB7 DB6 DB5 DB4
IR7 IR6 IR5 IR4
IR3 IR2 IR1 IR0
Busy
No Busy ADC6 ADC5 ADC4 Reading BF (Busy Flag) and ADC (Address Counter)
ADC3 ADC2 ADC1 ADC0
DR7 DR6 DR5 DR4
DR3 DR2 DR1 DR0
Writing In IR (Instruction Register)
Writing In DR (Data Register)
Figure 3 4-Bit Data Transfer
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Semiconductor Serial Interface Mode
ML9044
In the Serial I/F Mode, the ML9044 interfaces with the CPU via the CS, SHT, SI and SO pins. Writing and reading operations are executed in units of 16 bits after the CS signal falls down. If the CS signal rises up before the completion of 16-bit unit access, this access is ignored. When the BF bit is "1", the ML9044 cannot accept any other instructions. Before inputting a new instruction, check that the BF bit is "0". Any access when the BF bit is "1" is ignored. Data format is LSB-first. Examples of Access in the Serial I/F Mode 1) WRITE MODE
CS 1
SHT
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SI
1
1
1
1
1
R/W RS0 RS1
D0
D1
D2
D3
D4
D5
D6
D7
SO
2) READ MODE
CS 1
SHT
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SI
1
1
1
1
1
R/W
RS0 RS1
SO
D0
D1
D2
D3
D4
D5
D6
D7
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Semiconductor Instruction Codes Table of Instruction Codes
Instruction Code RS1 RS0 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 0 0 0 0 0 0 0 0 0 1 Function Clears all the displayed digits of the LCD and Display Clear sets the DDRAM address 0 in the address counter. The arbitrator data is cleared. Sets the DDRAM address 0 in the address Cursor Home 1 0 0 0 0 0 0 0 0 1 * counter and shifts the display back to the original. The content of the DDRAM remains unchanged. Determines the direction of movement of Entry Mode Setting 1 0 0 0 0 0 0 0 1 I/D S the cursor and whether or not to shift the display. This instruction is executed when data is written or read. Sets LCD display ON/OFF (D), cursor Displya ON/OFF Control 1 0 0 0 0 0 0 1 D C B ON/OFF or cursor-position character blinking ON/OFF. Cursor/Display Shift 1 0 0 0 0 0 1 S/C R/L * * Moves the cursor or shifts the display without changing the content of the DDRAM. Sets the interface data length (DL), the Function Setting 1 0 0 0 0 1 DL N F * * number of display lines (N) or the type of character font (F). Sets on CGRAM address. After that, CGRAM Address Setting 1 0 0 0 1 ACG CGRAM data is transferred to and from the CPU. Sets a DDRAM address. After that DDRAM DDRAM Address Setting 1 0 0 1 ADD data is transferred to and from the CPU. Reads the Busy Flag (indicating that the Busy Flag/Address Read 1 0 1 BF ADC ML9044 is operating) and the content of the address counter. Writes data in DDRAM, ABRAM or CGRAM. Reads data from DDRAM, ABRAM or CGRAM.
ML9044
Execution Time f = 270kHz 1.52 ms
1.52 ms
37 ms
37 ms
37 ms
37 ms
37 ms
37 ms
0 ms
RAM Data Write RAM Data Read Arbitrator Display Line Set Contrast Control Data Write Contrast Control Data Read
1 1 0 0 0
1 1 0 0 0
0 1 0 0 1 0 0 0 0 0 0 0 1 0
WRITE DATA READ DATA 0 0 0 1 AS
37 ms 37 ms 37 ms 37 ms 37 ms
Sets the arbitrator display line. Writes data to control the contrast of the LCD. Reads data to control the contrast of the LCD. Sets an ABRAM address. After that
WRITE (Contrast Data) DATA READ (Contrast Data) DATA
ABRAM address setting
0
0
0
0
1
1
AAB I/D = "0" (Decrement) S/C = "0" (Moves the cursor.) R/L = "0" (Left shift) DL = "0" (4-bit data) N = "0" (1 line) F = "0" (5 7 dots) BF = "0" (Ready to accept an instruction)
ABRAM data is transferred to and from the CPU.
DD RAM : Display data RAM CG RAM : Character generator RAM ABRAM : Arbitrator data RAM ACG : CGRAM address ADD : DDRAM address (Corresponds to the cursor address) AAB : ABRAM address ADC : Address counter (Used by DDRAM, ABRAM and CGRAM)
37 ms The execution time is dependent upon frequencies
--
I/D = "1" (Increment) S = "1" (Shifts the display.) S/C = "1" (Shifts display.) R/L = "1" (Right shift) D/L = "1" (8-bit data) N = "1" (2 lines) F = "1" (5 10 dots) BF = "1" (Busy) B = "1" C = "1" D = "1" AS = "1"
(Enables blinking.) (Displyas the corsor.) (Displays a character pattern.) (Arbitrator Displays arbitrator AS = "0" (Arbitrator Displays on the upper line) arbitrator on the lower line)
: Don't Care 32/54
Semiconductor
ML9044
Instruction Codes An instruction code is a signal sent from the CPU to access the ML9044. The ML9044 starts operation as instructed by the code received. The busy status of the ML9044 is rather longer than the cycle time of the CPU, since the internal processing of the ML9044 starts at a timing which does not affect the display on the LCD. In the busy status (Busy Flag is "1"), the ML9044 executes the Busy Flag Read instruction only. Therefore, the CPU should ensure that the Busy Flag is "0" before sending an instruction code to the ML9044. 1) Display Clear
RS1 Instruction Code : 1 RS0 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 0 DB1 0 DB0 1
When this instruction is executed, the LCD display including arbitrator display is cleared and the I/D entry mode is set to "Increment". The value of "S" (Display shifting) remains unchanged. The position of the cursor or blink being displayed moves to the left end of the LCD (or the left end of the line 1 in the 2-line display mode). Note: All DDRAM and ABRAM data turn to "20" and "00" in hexadecimal, respectively. The value of the address counter (ADC) turns to the one corresponding to the address "00" (hexadecimal) of the DDRAM. The execution time of this instruction is 1.52 ms (maximum) at an oscillation frequency of 270 kHz.
2) Cursor Home
RS1 Instruction code: 1 RS0 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 0 DB1 1 DB0
: Don't Care
When this instruction is executed, the cursor or blink position moves to the left end of the LCD (or the left end of line 1 in the 2-line display mode). If the display has been shifted, the display returns to the original display position before shifting. Note: The value of the address counter (ADC) goes to the one corresponding to the address "00" (hexadecimal) of the DDRAM). The execution time of this instruction is 1.52 ms (maximum) at an oscillation frequency of 270 kHz.
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Semiconductor 3) Entry Mode Setting
RS1 Instruction code: 1 RS0 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 1 DB1 I/D
ML9044
DB0 S
(1) When the I/D is set, the cursor or blink shifts to the right by 1 character position (ID= "1"; increment) or to the left by 1 character position (I/D= "0"; decrement) after an 8-bit character code is written to or read from the DDRAM. At the same time, the address counter (ADC) is also incremented by 1 (when I/D = "1"; increment) or decremented by 1 (when I/D = "0"; decrement). After a character pattern code is written to or read from the CGRAM, the address counter (ADC) is incremented by 1 (when I/D = "1"; increment) or decremented by 1 (when I/D = "0"; decrement). Also after data is written to or read from the ABRAM, the address counter (ADC) is incremented by 1 (when I/D = "1"; increment) or decremented by 1 (when I/D = "0"; decrement). (2) When S = "1", the cursor or blink stops and the entire display shifts to the left (I/D = "1") or to the right (I/D = "0") by 1 character position after a character code is written to the DDRAM. In the case of S = "1",when a character code is read from the DDRAM, when a character pattern data is written to or read from the CGRAM or when data is written to or read from the ABRAM, normal read/write is carried out without shifting of the entire display. (The entire display does not shift, but the cursor or blink shifts to the right (I/D = "1") or to the left (I/D = "0") by 1 character position.) When S = "0", the display does not shift, but normal write/read is performed. Note: The execution time of this instruction is 37 ms (maximum) at an oscillation frequency of 270 kHz. 4) Display Mode Setting
RS1 Instruction code: 1 RS0 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 1 DB2 D DB1 C DB0 B
(1) The "D" bit (DB2) of this instruction determines whether or not to display character patterns on the LCD. When the "D" bit is "1", character patterns are displayed on the LCD. When the "D" bit is "0", character patterns are not displayed on the LCD and the cursor/blink setting is also canceled. Note: Unlike the Display Clear instruction, this instruction does not change the character code in the DDRAM and ABRAM.
(2 ) When the "C" bit (DB1) is "0", the cursor turns off. When both the "C" and "D" bits are "1", the cursor turns on. (3) When the "B" bit (DB0) is "0", blinking is canceled. When both the "B" and "D" bits are "1", blinking is performed. In the Blinking mode, all dots including those of the cursor, the character pattern and the cursor are alternately displayed. Note: The execution time of this instruction is 37 ms (maximum) at an oscillation frequency of 270kHz. 34/54
Semiconductor 5) Cursor/Display Shift
RS1 Instruction code: 1 RS0 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 1 DB3 S/C DB2 R/L DB1
ML9044
DB0
: FDon't Care
S/C = "0", R/L = "0" This instruction shifts left the cursor and blink positions by 1 (decrements the content of the ADC by 1). S/C = "0", R/L = "1" This instruction shifts right the cursor and blink positions by 1 (increments the content of the ADC by 1). S/C = "1", R/L = "0" This instruction shifts left the entire display by 1 character position. The cursor and blink positions move to the left together with the entire display. The Arbitrator display is not shifted. (The content of the ADC remains unchanged.) S/C = "1", R/L = "1" This instruction shifts right the entire display by 1 character position. The cursor and blink positions move to the right together with the entire display. The Arbitrator display is not shifted. (The content of the ADC remains unchanged.) In the 2-line mode, the cursor or blink moves from the first line to the second line when the cursor at digit 40 (27; hex) of the first line is shifted right. When the entire display is shifted, the character pattern, cursor or blink will not move between the lines (from line 1 to line 2 or vice versa). Note: The execution time of this instruction is 37 ms at an oscillation frequency (OSC) of 270 kHz. 6) Function Setting
RS1 Instruction code: 1 RS0 0 R/W 0 DB7 0 DB6 0 DB5 1 DB4 DL DB3 N DB2 F DB1 DB0
: Don't Care
(1) When the "DL" bit (DB4) of this instruction is "1", the data transfer to and from the CPU is performed once by the use of 8 bits DB7 to DB0. When the "DL" bit (DB4) of this instruction is "0", the data transfer to and from the CPU is performed twice by the use of 4 bits DB7 to DB4. (2) The 2-line display mode is selected when the "N" bit (DB3) of this instruction is "1". The 1- line display mode is selected when the "N" bit is "0". (3) The character font represented by 5 7 dots is selected when the "F" bit (DB2) of this instruction is "1". The character font represented by 5 10 dots is selected when the "F" bit is "1" and the "N" bit is "0". After the ML9044 is powered on, this initial setting should be carried out before execution of any instruction except the Busy Flag Read. After this initial setting, no instructions other than the DL Set instruction can be executed. In the Serial I/F Mode, DL setting is ignored.
N 0 0 1 1 F 0 1 0 1 Number of display lines 1 1 2 2 Font size 57 510 57 57 Duty 1/9 1/12 1/17 1/17 Number of biases 4 4 5 5 Number of common signals 9 12 17 17
Note:
The execution time of this instruction is 37 ms at an oscillation frequency (OSC) of 270 kHz. 35/54
Semiconductor 7) CGRAM Address Setting
RS1 Instruction code: 1 RS0 0 R/W 0 DB7 0 DB6 1 DB5 C5 DB4 C4 DB3 C3 DB2 C2 DB1 C1
ML9044
DB0 C0
This instruction sets the character data corresponding to the CGRAM address represented by the bits C5 to C0 (binary). The CGRAM addresses are valid until DDRAM or ABRAM addresses are set. The CPU writes or reads character patterns starting from the one represented by the CGRAM address bits C5 to C0 set in the instruction code at that time. Note: The execution time of this instruction is 37 ms at an oscillation frequency (OSC) of 270 kHz.
8) DDRAM Address Setting
RS1 Instruction code: 1 RS0 0 R/W 0 DB7 1 DB6 D6 DB5 D5 DB4 D4 DB3 D3 DB2 D2 DB1 D1 DB0 D0
This instruction sets the character data corresponding to the DDRAM address represented by the bits D6 to D0 (binary). The DDRAM addresses are valid until CGRAM or ABRAM addresses are set. The CPU writes or reads character patterns starting from the one represented by the DDRAM address bits D6 to D0 set in the instruction code at that time. In the 1-line mode (the "N" bit is "1"), the DDRAM address represented by bits D6 to D0 (binary) should be in the range "00" to "4F" in hexadecimal. In the 2-line mode (the "N" bit is "2"), the DDRAM address represented by bits D6 to D0 (binary) should be in the range "00" to "27" or "40" to "67" in hexadecimal. If an address other than above is input, the ML9044 cannot properly write a character code in or read it from the DDRAM. Note: The execution time of this instruction is 37 ms at an oscillation frequency (OSC) of 270 kHz.
9) DDRAM/ABRAM/CGRAM Data Write
RS1 Instruction code: 1 RS0 1 R/W 0 DB7 E7 DB6 E6 DB5 E5 DB4 E4 DB3 E3 DB2 E2 DB1 E1 DB0 E0
This instruction writes data represented by bits E7 to E0 (binary) to DDRAM, ABRAM or CGRAM. After data is written, the cursor, blink or display shifts according to the Cursor/Display Shift instruction (see 5)). Note: The execution time of this instruction is 37 ms at an oscillation frequency (OSC) of 270 kHz.
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Semiconductor 10) Busy Flag/Address Counter Read (Execution time: 1 ms)
RS1 Instruction code: 1 RS0 0 R/W 1 DB7 BF DB6 O6 DB5 O5 DB4 O4 DB3 O3 DB2 O2 DB1 O1
ML9044
DB0 O0
The "BF" bit (DB7) of this instruction tells whether the ML9044 is busy in internal operation (BF = "1") or not (BF = "0"). When the "BF" bit is "1", the ML9044 cannot accept any other instructions. Before inputting a new instruction, check that the "BF" bit is "0". When the "BF" bit is "0", the ML9044 outputs the correct value of the address counter. The value of the address counter is equal to the DDRAM, ABRAM or CGRAM address. Which of the DDRAM, ABRAM and CGRAM addresses is set in the counter is determined by the preceding address setting. When the "BF" bit is "1", the value of the address counter is not always correct because it may have been incremented or decremented by 1 during internal operation. 11) DDRAM/ABRAM/CGRAM Data Read
RS1 Instruction code: 1 RS0 1 R/W 1 DB7 P7 DB6 P6 DB5 P5 DB4 P4 DB3 P3 DB2 P2 DB1 P1 DB0 P0
A character code (P7 to P0) is read from the DDRAM, Display-ON data (P7 to P0) from the ABRAM or a character pattern (P7 to P0) from the CGRAM. The DDRAM, ABRAM or CGRAM is selected at the preceding address setting. After data is read, the address counter (ADC) is incremented or decremented as set by the Transfer Mode Setting instruction (see 3). Note: Conditions for reading correct data
(1) The DDRAM, ABRAM or CGRAM Setting instruction is input before this data read instruction is input. (2) When reading a character code from the DDRAM, the Cursor/Display Shift instruction (see 5) is input before this Data Read instruction is input. (3) When two or more consecutive RAM Data Read instructions are executed, the following read data is correct. Correct data is not output under conditions other than the cases (1), (2) and (3) above. Note: The execution time of this instruction is 37 ms at an oscillation frequency (OSC) of 270 kHz.
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Semiconductor Expansion Instruction Codes
ML9044
The busy status of the ML9044 is rather longer than the cycle time of the CPU, since the internal processing of the ML9044 starts at a timing which does not affect the display on the LCD. In the busy status (Busy Flag is "1"), the ML9041 executes the Busy Flag Read instruction only. Therefore, the CPU should ensure that the Busy Flag is "0" before sending an expansion instruction code to the ML9044. 1) Arbitrator Display Line Set
RS1 Exparsion Instruction codes: 0 RS0 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 0 DB1 1 DB0 AS
This expansion instruction code sets the Arbitrator display line. The relationship between the status of this bit and the common outputs is as follows:
CSR L L L L L L H H H H H H duty 1/9 1/9 1/12 1/12 1/17 1/17 1/9 1/9 1/12 1/12 1/17 1/17 AS bit L H L H L H L H L H L H Shift direction COM1 AE COM9 COM2 AE COM9, COM1 COM1 AE COM12 COM2 AE COM12, COM1 COM1 AE COM17 COM2 AE COM17, COM1 COM9 AE COM1 COM8 AE COM1, COM9 COM12 AE COM1 COM11 AE COM1, COM12 COM17 AE COM1 COM16 AE COM1, COM17 Arbitrator's comon pin COM9 COM1 COM12 COM1 COM17 COM1 COM1 COM9 COM1 COM12 COM1 COM17
2) Contrast Adjusting Data Write
RS1 Exparsion Instraction codes: 0 RS0 0 R/W 0 DB7 0 DB6 0 DB5 1 DB4 F4 DB3 F3 DB2 F2 DB1 F1 DB0 F0
This instruction writes contrast adjusting data (F4 to F0) to the contrast register. After contrast adjusting data is written in the register, the potential (VLCD) output to the V5 pin varies according to the data written. The VLCD becomes maximum when the content of the contrast register is "1F" (hexadecimal) and becomes minimum when it is "00" (hexadecimal). Note: The execution time of this instruction is 37 ms at an oscillation frequency (OSC) of 270 kHz.
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Semiconductor 3) Contrast Adjusting Data Read
RS1 Exparsion Instruction code: 0 RS0 0 R/W 1 DB7 0 DB6 0 DB5 0 DB4 G4 DB3 G3 DB2 G2
ML9044
DB1 G1
DB0 G0
This instruction reads contrast adjusting data (G4 to G0) from the contrast register. Note: The execution time of this instruction is 37 ms at an oscillation frequency (OSC) of 270 kHz. 4) ABRAM Address Setting
RS1 Exparsion Instruction code: 0 RS0 0 R/W 1 DB7 0 DB6 1 DB5 1 DB4 H4 DB3 H3 DB2 H2 DB1 H1 DB0 H0
This instruction sets the character data corresponding to the ABRAM address represented by the bits H4 to H0 (binary). The ABRAM addresses are valid until CGRAM or DDRAM addresses are set. The CPU writes or reads character patterns starting from the one represented by the ABRAM address bits H4 to H0 set in the instruction code at that time. The ABRAM address represented by bits H4 to H0 (binary) should be in the range "00" to "13" in hexadecimal. If an address other than above is input, the ML9044 cannot properly write a character code in or read it from the DDRAM. Note: The execution time of this instruction is 37 ms at an oscillation frequency (OSC) of 270 kHz.
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Semiconductor LCD Drive Waveforms
ML9044
The COM and SEG waveforms (AC signal waveforms for display) vary according to the duty (1/ 9, 1/12 and 1/17 duties). See 1) to 3) below. The relationship between the duty ratio and the frame frequency is as follows:
Duty ratio 1/9 1/12 1/17 Frame Frequency 75.0Hz 56.3Hz 79.4Hz
Note:
At an oscillation frequency (OSC) of 270 kHz
(1) Driving the LCD of one 24-character line (1/9 duty, CSR = L, AS = 0) under the conditions of the 1-line display mode and the character font of 5 7 dots
COM1 Character COM8 COM9 Cursor Arbitrator
SEG1 ML9044
SEG120
* COM10 to COM17 output Display-OFF common signals.
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Semiconductor
ML9044
(2) Driving the LCD of one 24-character line (1/12 duty, CSR = L, AS = 0) under the conditions of the 1-line display mode and the character font of 5 10 dots
COM1 Character COM11 COM12
Cursor Arbitrator SEG1 MSM9044 SEG120
* COM13 to COM17 output Display-OFF common signals. (3) Driving the LCD of two 24-character line (1/17 duty, CSR = L, AS = 0) under the conditions of the 2-line display mode and the character font of 5 7 dots
COM1 Character COM8 COM9 Character COM16 COM17 Cursor Arbitrator Cursor
SEG1 MSM9044
SEG120
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Semiconductor
ML9044
EXAMPLES OF VLCD GENERATION CIRCUITS
* With 1/4bias, a built-in contrast adjusting circuit and a voltage multiplier
ML9044
VDD V1 V2 V3A V3B V4 V5 V5IN VC VCC VIN BEB
Reference potential for voltage multiplien
* With 1/5 bias, a built-in contrast adjusting circuit and the V5 level input from an external circuit
ML9044
VDD V1 V2 V3A V3B V4 V5 V5IN VC VCC VIN BEB V5 level
42/54
Semiconductor 1) COM and SEG Waveforms on 1/9 Duty
891234
COM1 (CSR = L, AS = L) COM2 (CSR = L, AS = H) COM9 (CSR = H, AS = L) COM8 (CSR = H, AS = H) (first character line)
ML9044
7891234
78912
VDD V1 V2, V3B V4 V5
1 frame
COM2 (CSR = L, AS = L) COM3 (CSR = L, AS = H) COM8 (CSR = H, AS = L) COM7 (CSR = H, AS = H) (second character line)
VDD V1 V2, V3B V4 V5 VDD V1 V2, V3B V4 V5 VDD V1 V2, V3B V4 V5 VDD V1 V2, V3B V4 V5
Display turning-off waveform
COM8 (CSR = L, AS = L) COM9 (CSR = L, AS = H) COM2 (CSR = H, AS = L) COM1 (CSR = H, AS = H) (cursor line)
COM9 (CSR = L, AS = L) COM1 (CSR = L, AS = H) COM1 (CSR = H, AS = L) COM9 (CSR = H, AS = H) (arbitrator line)
COM10 to COM17
SEG
VDD V1 V2, V3B V4 V5
Display turning-on waveform
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Semiconductor 2) COM and SEG Waveforms on 1/12 Duty
11 12 1 2 3 4 5 6
COM1 (CSR = L, AS = L) COM2 (CSR = L, AS = H) COM12 (CSR = H, AS = L) COM11 (CSR = H, AS = H) (first character line)
ML9044
9 10 11 12 1 2 3 4 5 6
VDD V1 V2, V3B V4 V5
1 frame
COM2 (CSR = L, AS = L) COM3 (CSR = L, AS = H) COM11 (CSR = H, AS = L) COM10 (CSR = H, AS = H) (second character line)
VDD V1 V2, V3B V4 V5 VDD V1 V2, V3B V4 V5 VDD V1 V2, V3B V4 V5 VDD V1 V2, V3B V4 V5
Display turning-off waveform
COM11 (CSR = L, AS = L) COM12 (CSR = L, AS = H) COM2 (CSR = H, AS = L) COM1 (CSR = H, AS = H) (cursor line)
COM12 (CSR = L, AS = L) COM1 (CSR = L, AS = H) COM1 (CSR = H, AS = L) COM12 (CSR = H, AS = H) (arbitrator line)
COM13 to COM17
SEG
VDD V1 V2, V3B V4 V5
Display turning-on waveform
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Semiconductor 3) COM and SEG Waveforms on 1/17 Duty
16 17 1 2 3 4 5 6 7 8 9 10 11 12 13
COM1 (CSR = L, AS = L) COM2 (CSR = L, AS = H) COM17 (CSR = H, AS = L) COM16 (CSR = H, AS = H) (first character line)
ML9044
16 17 1 2 3 4
V3A (V3B) V4 V5
VDD V1 V2
1 frame
COM2 (CSR = L, AS = L) COM3 (CSR = L, AS = H) COM16 (CSR = H, AS = L) COM15 (CSR = H, AS = H) (second character line)
V3A (V3B) V4 V5
VDD V1 V2
COM16 (CSR = L, AS = L) COM17 (CSR = L, AS = H) COM2 (CSR = H, AS = L) COM1 (CSR = H, AS = H) (corsor line)
V3A (V3B) V4 V5
VDD V1 V2
COM17 (CSR = L, AS = L) COM1 (CSR = L, AS = H) COM1 (CSR = H, AS = L) COM17 (CSR = H, AS = H) (arbitrator line)
V3A (V3B) V4 V5
Display turning-off waveform
VDD V1 V2
SEG
V3A (V3B) V4 V5
Display turning-on waveform
VDD V1 V2
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Semiconductor Initial Setting of Instructions
ML9044
(a) Data transfer from and to the CPU using 8 bits of DB0 to DB7 1) Turn on the power. 2) Wait for 15 ms or more after VDD has reached 2.5V or higher. 3) Set "8 bits" with the Function Setting instruction. 4) Wait for 4.1 ms or more. 5) Set "8 bits" with the Function Setting instruction. 6) Wait for 100 ms or more. 7) Set "8 bits" with the Function Setting instruction. 8) Check the Busy Flag for No Busy (or wait for 100 ms or more). 9) Set "8 bits", "Number of LCD lines" and "Font size" with the Function Setting instruction. (After this, the number of LCD lines and the font size cannot be changed.) 10) Check the Busy Flag for No Busy. 11) Execute the Display Mode Setting Instruction, Display Clear Instruction, Entry Mode Setting instruction and Arbitrator Display Line Setting Instruction. 12) Check the Busy Flag for No Busy. 13) Initialization is completed. An example of instruction code for 3), 5) and 7)
RS1 1 RS0 0 R/W 0 DB7 0 DB6 0 DB5 1 DB4 1 DB3 DB2 DB1 DB0
: Don't Care
(b) Data transfer from and to the CPU using 8 bits of DB4 to DB7 1) Turn on the power. 2) Wait for 15 ms or more after VDD has reached 2.5V or higher. 3) Set "8 bits" with the Function Setting instruction. 4) Wait for 4.1 ms or more. 5) Set "8 bits" with the Function Setting instruction. 6) Wait for 100 ms or more. 7) Set "8 bits" with the Function Setting instruction. 8) Check the Busy Flag for No Busy (or wait for 100 ms or longer). 9) Set "4 bits" with the Function Setting instruction. 10) Wait for 100 ms or longer. 11) Set "4 bits", "Number of LCD lines" and "Font size" with the Initial Setting instruction. (After this, the number of LCD lines and the font size cannot be changed.) 12) Check the Busy Flag for No Busy. 13) Execute the Display Mode Setting Instruction, Display Clear Instruction, Entry Mode Setting instruction and Arbitrator Display Line Setting Instruction 14) Check the Busy Flag for No Busy. 15) Initialization is completed. An example of instruction code for 3), 5) and 7)
RS1 1 RS0 0 R/W 0 DB7 0 DB6 0 DB5 1 DB4 1
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Semiconductor An example of instruction code for 9)
RS1 1 RS0 0 R/W 0 DB7 0 DB6 0 DB5 1 DB4 0
ML9044
*: In 13), check the Busy Flag for No Busy before executing each instruction. (c) Data transfer from and to the CPU using the serial I/F 1) Turn on the power. 2) Wait for 15 ms or more after VDD has reached 2.5V or higher. 3) Set "Number of LCD lines" and "Font size" with the Function Setting Instruction. 4) Execute the Display Mode Setting Instruction, the Display Clear Instruction, the Entry Mode Instruction and the Arbitrator Display Line Setting Instruction. 5) Check the busy flag for No Busy. 6) Initialization is completed. *: In 3) and 4), check the Busy Flag for No Busy before executing each instruction.
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Semiconductor
ML9044
Relationship Between Character Codes and Character patterns
00H 08H 10H 18H 20H 28H 30H 38H
01H
09H
11H
19H
21H
29H
31H
39H
02H
0AH
12H
1AH
22H
2AH
32H
3AH
03H
0BH
13H
1BH
23H
2BH
33H
3BH
04H
0CH
14H
1CH
24H
2CH
34H
3CH
05H
0DH
15H
1DH
25H
2DH
35H
3DH
06H
0EH
16H
1EH
26H
2EH
36H
3EH
07H
0FH
17H
1FH
27H
2FH
37H
3FH
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Semiconductor
ML9044
40H
48H
50H
58H
60H
68H
70H
78H
41H
49H
51H
59H
61H
69H
71H
79H
42H
4AH
52H
5AH
62H
6AH
72H
7AH
43H
4BH
53H
5BH
63H
6BH
73H
7BH
44H
4CH
54H
5CH
64H
6CH
74H
7CH
45H
4DH
55H
5DH
65H
6DH
75H
7DH
46H
4EH
56H
5EH
66H
6EH
76H
7EH
47H
4FH
57H
5FH
67H
6FH
77H
7FH
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Semiconductor
ML9044
80H
88H
90H
98H
A0H
A8H
B0H
B8H
81H
89H
91H
99H
A1H
A9H
B1H
B9H
82H
8AH
92H
9AH
A2H
AAH
B2H
BAH
83H
8BH
93H
9BH
A3H
ABH
B3H
BBH
84H
8CH
94H
9CH
A4H
ACH
B4H
BCH
85H
8DH
95H
9DH
A5H
ADH
B5H
BDH
86H
8EH
96H
9EH
A6H
AEH
B6H
BEH
87H
8FH
97H
9FH
A7H
AFH
B7H
BFH
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Semiconductor
ML9044
C0H
C8H
D0H
D8H
E0H
E8H
F0H
F8H
C1H
C9H
D1H
D9H
E1H
E9H
F1H
F9H
C2H
CAH
D2H
DAH
E2H
EAH
F2H
FAH
C3H
CBH
D3H
DBH
E3H
EBH
F3H
FBH
C4H
CCH
D4H
DCH
E4H
ECH
F4H
FCH
C5H
CDH
D5H
DDH
E5H
EDH
F5H
FDH
C6H
CEH
D6H
DEH
E6H
EEH
F6H
FEH
C7H
CFH
D7H
DFH
E7H
EFH
F7H
FFH
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Semiconductor
ML9044
PAD CONFIGURATION
Pad Layout Chip Size Chip Thickness Bump Size (1) Bump Size (2)
182 183 Y
: 10.62 2.55mm : 62520mm : 72 72mm : 54 96mm
63 62 X
189 1 55
56
Pad Coordinates
Pad 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Symbol V1 V2 V3A V3B V4 V5 V5IN VCC VC VIN BEB VDD CSR SSR P/S VSS DB7 DB6 DB5 DB4 X (mm) -5103 -4914 -4725 -4536 -4347 -4158 -3969 -3780 -3591 -3402 -3213 -3024 -2835 -2646 -2457 -2268 -2079 -1890 -1701 -1512 Y (mm) -1099.8 -1099.8 -1099.8 -1099.8 -1099.8 -1099.8 -1099.8 -1099.8 -1099.8 -1099.8 -1099.8 -1099.8 -1099.8 -1099.8 -1099.8 -1099.8 -1099.8 -1099.8 -1099.8 -1099.8 Pad 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Symbol DB3 DB2 DB1 DB0 E R/W RS0 RS1 SO SI SHT CS OSC2 OSCR OSC1 T3 T2 T1 COM1 COM2 X (mm) -1323 -1134 -945 -756 -567 -378 -189 0 189 378 567 756 945 1134 1323 1512 1701 1890 2079 2268 Y (mm) -1099.8 -1099.8 -1099.8 -1099.8 -1099.8 -1099.8 -1099.8 -1099.8 -1099.8 -1099.8 -1099.8 -1099.8 -1099.8 -1099.8 -1099.8 -1099.8 -1099.8 -1099.8 -1099.8 -1099.8
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Semiconductor
ML9044
Pad 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
Symbol COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY SEG120 SEG119 SEG118 SEG117 SEG116 SEG115 SEG114 SEG113 SEG112 SEG111 SEG110 SEG109 SEG108 SEG107 SEG106 SEG105 SEG104 SEG103
X (mm) 2457 2646 2835 3024 3213 3402 3591 3780 3969 4158 4347 4536 4725 4914 5103 5184 5184 5184 5184 5184 5184 5184 4998 4914 4830 4746 4662 4578 4494 4410 4326 4242 4158 4074 3990 3906 3822 3738 3654 3570
Y (mm) -1099.8 -1099.8 -1099.8 -1099.8 -1099.8 -1099.8 -1099.8 -1099.8 -1099.8 -1099.8 -1099.8 -1099.8 -1099.8 -1099.8 -1099.8 -720 -480 -240 0 240 480 720 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8
Pad 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
Symbol SEG102 SEG101 SEG100 SEG99 SEG98 SEG97 SEG96 SEG95 SEG94 SEG93 SEG92 SEG91 SEG90 SEG89 SEG88 SEG87 SEG86 SEG85 SEG84 SEG83 SEG82 SEG81 SEG80 SEG79 SEG78 SEG77 SEG76 SEG75 SEG74 SEG73 SEG72 SEG71 SEG70 SEG69 SEG68 SEG67 SEG66 SEG65 SEG64 SEG63
X (mm) 3486 3402 3318 3234 3150 3066 2982 2898 2814 2730 2646 2562 2478 2394 2310 2226 2142 2058 1974 1890 1806 1722 1638 1554 1470 1386 1302 1218 1134 1050 966 882 798 714 630 546 462 378 294 210
Y (mm) 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8
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Semiconductor
ML9044
Pad 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155
Symbol SEG62 SEG61 SEG60 SEG59 SEG58 SEG57 SEG56 SEG55 SEG54 SEG53 SEG52 SEG51 SEG50 SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28
X (mm) 126 42 -42 -126 -210 -294 -378 -462 -546 -630 -714 -798 -882 -966 -1050 -1134 -1218 -1302 -1386 -1470 -1554 -1638 -1722 -1806 -1890 -1974 -2058 -2142 -2226 -2310 -2394 -2478 -2562 -2646 -2730
Y (mm) 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8
Pad 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189
Symbol SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY
X (mm) -2814 -2898 -2982 -3066 -3150 -3234 -3318 -3402 -3486 -3570 -3654 -3738 -3822 -3906 -3990 -4074 -4158 -4242 -4326 -4410 -4494 -4578 -4662 -4746 -4830 -4914 -4998 -5184 -5184 -5184 -5184 -5184 -5184 -5184
Y (mm) 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 720 480 240 0 -240 -480 -720
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E2Y0002-29-62
NOTICE
1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. No part of the contents contained herein may be reprinted or reproduced without our prior permission. MS-DOS is a registered trademark of Microsoft Corporation.
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Copyright 1999 Oki Electric Industry Co., Ltd.
Printed in Japan

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